Electrical and Computer Engineering
Dr. Shubu Mukherjee
Cavium's Multicore Processors for the Zettabyte Era
Tuesday, September 10, 2013
to 5:00 PM
1064 George R. Brown Hall
6100 Main St
Houston, Texas, USA
The explosion in global internet traffic towards zettabytes per year is posing a significant challenge to the design of multicore chips used for network and data center processing. The design of processor cores used in such multicore chips has always required a balance of performance and efficiency in power, area, and complexity. The emergence of multicore SoCs (systems on a chip) armed with accelerators for packet processing and cloud acceleration has shifted this balance from solely single-thread performance to a combination of single-thread performance and efficient parallel processing. This shift requires a new style of cores with short and deterministic pipelines, caches and memory systems optimized for low latency and high bandwidth, and an accelerator architecture that scales to 48+ cores on a chip. This talk will demonstrate how continuously emerging application demands has shaped the fundamental principles behind Cavium's processor cores and supporting on-chip accelerators.
Host: Peter J. Varman
Biography of Dr. Shubu Mukherjee:
Dr. Shubu Mukherjee is one of Cavium Inc's Distinguished Engineers and lead architects for the OCTEON-III and Thunder family of processors. Shubu is the winner of the ACM SIGARCH Maurice-Wilkes award, a Fellow of ACM, a Fellow of IEEE, and the author of the book, “Architecture Design for Soft Errors”. Shubu holds 33 patents and has written over 50 technical papers in top architecture conference and journals. Before joining Cavium in May 2010, Shubu worked at Intel for 9 years and Compaq for 3 years. He received his MS and PhD from the University of Wisconsin-Madison and his B.Tech., from the Indian Institute of Technology, Kanpur.