Rice University

Events at Rice

Seminar

Electrical and Computer Engineering
Dean of Engineering
Faculty Host: Lin Zhong

Speaker: Matt Sinclair
PhD Candidate in Computer Science
UIUC

ECE Seminar Series: Efficient Memory Hierarchies for Heterogeneous Systems (698/699)

Wednesday, March 22, 2017
4:00 PM  to 5:00 PM

1064  Duncan Hall
Rice University
6100 Main St
Houston, Texas, USA

As the benefits from transistor scaling diminish, specialized accelerators and heterogeneous computing are becoming increasingly important because they can significantly improve performance and energy efficiency for specific applications. An efficient and easy-to-program memory and communication architecture is critical to fulfilling the promise of such systems. Traditionally, accelerators in heterogeneous systems use discrete address spaces and employ specialized memories, e.g., scratchpads, for specific access patterns. However, for emerging workloads in domains such as graph analytics, these attributes make heterogeneous systems both difficult to program and inefficient. My thesis uses cross-cutting research that rethinks the software, hardware, and hardware-software interface to make heterogeneous systems easier to program and more efficient. Underlying my work is the efficient support of a global address space across all accelerator memories (to make programming easier), an efficient cache coherence protocol (to improve the efficiency of the hardware), and a familiar memory consistency model (to provide an appropriate hardware-software interface). Overall, my research enables more application domains to exploit the efficiency benefits of specialization and heterogeneity.

Biography of Matt Sinclair:
Matt Sinclair is a doctoral candidate in the Department of Computer Science at the University of Illinois at Urbana-Champaign. He is interested in computer architecture and systems, with a current focus on building efficient memory hierarchies for heterogeneous systems. His papers at the 2015 International Symposium on Computer Architecture (ISCA) and 2015 International Symposium on Microarchitecture (MICRO) were recognized as 2016 IEEE Micro Top Picks Honorable Mentions. He is the recipient of a Qualcomm Innovation Fellowship, two Mavis Future Faculty Fellowships, the Feng Chen Memorial Award, the W.J. Poppelbaum Award, and a Saburo Muroga Fellowship. He was also selected to attend and present his research at the 2016 Heidelberg Laureate Forum. He received a BS in Computer Science with Honors & Computer Engineering (2009) and a MS in Electrical Engineering (2011) from the University of Wisconsin-Madison.



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