Electrical and Computer Engineering
Dean of Engineering
Staff Research Scientist
Circuit Research Lab
ECE Seminar Series: Energy Efficient Memories for the Compute Continuum and Beyond, Jaydeep Kulkarni (698/699)
Wednesday, March 29, 2017
to 5:00 PM
1064 Duncan Hall
6100 Main St
Houston, Texas, USA
With the rapid advances in computing systems spanning from billions of IoTs (Internet of Things) to high performance exascale supercomputers, energy efficient design is an absolute must. Moreover, with the emergence of neural network accelerators for machine learning applications, there is a growing need for large capacity memories. It is estimated that by 2040, around 1 Trillion computing devices will be deployed generating millions of Zettabytes (1 Zetta = 1021) consuming tens of Zetta-joules of compute energy/year. These trends clearly indicate the paramount importance of energy efficient memories across the compute continuum and to cater storage needs for future workloads.
In this seminar, I will discuss the circuit solutions for realizing energy efficient memory arrays. Supply voltage scaling is the primary driver to reduce energy consumption. The minimum operating supply voltage (Vmin) of a compute block consisting of static CMOS datapath logic and memory arrays is typically limited by process variations in the memory bitcells using minimum sized transistors. I will present an overview of low power memory design using novel bitcell topologies (Schmitt Trigger SRAMs [JSSC’07, TVLSI’12]), Vmin-assist techniques (capacitive coupling, dual-Vcc design [ISSCC’12, VLSI’13]), and guardband reduction methods (ISSCC’15, JSSC’16). Voltage/Frequency (V/F) guardbands are applied to account for the worst-case dynamic variations such as voltage droops, temperature fluctuations, and aging-induced degradation. However, since most systems usually operate at nominal conditions, the fixed guardbands for infrequent dynamic variations significantly limit the best achievable performance and energy efficiency. I will dive deep into an adaptive and resilient array design featuring in-situ timing margin and timing error detector circuits to mitigate these V/F guardbands due to dynamic variations. The bitline sensing failures in the domino read path of a register file are converted into timing failures which are then captured at the output using double sampling mechanism. The proposed approach can enable a unified guardband reduction framework for logic + memory arrays operating on same voltage/frequency domain. Measurement results from a 22nm test-chip demonstrated 21% higher throughput with 67% improved energy efficiency.
I will conclude the seminar with my vision about the impact of memories on the next generation computing systems and share my recent work spanning across novel materials (III-V, correlated materials), emerging devices (TFET, MRAM, STT-RAM), architectures (mixed-cell cache), applications (neuromorphic computing, and alternative computing models (coupled oscillators). These cross-layer interactions across the hardware stack can truly harness the benefits of each of its components to realize future energy efficient systems for the data centric world.
Biography of Jaydeep Kulkarni:
Jaydeep Kulkarni received the Bachelor of Engineering (B.E.) degree from the University of Pune, India in 2002, the Master of Technology (M. Tech.) degree from the Indian Institute of Science (IISc) Bangalore, India in 2004 and Ph.D. degree from Purdue University, West Lafayette, IN, in 2009 all in electrical engineering. During 2004-05, he worked as a Design Engineer at Cypress Semiconductors, Bangalore and designed I/O circuits for micro-power SRAMs. He joined Circuit Research Lab (CRL) Intel Corporation, Hillsboro, OR in 2009, where he is currently working as a staff research scientist. His research is focused on energy efficient integrated circuits and systems, emerging nanotechnologies, and alternative computing models. He has filed 30 patents, published 2 book chapters and 55 papers in referred journals and conferences.
Dr. Kulkarni received 2004 best graduate student award from IISc Bangalore, two Semiconductor Research Corporation's (SRC) inventor recognition awards, 2008 ISLPED design contest award, 2008 Intel foundation Ph.D. fellowship award, 2008 SRC TECHCON best paper in session award, 2010 Purdue school of ECE outstanding doctoral dissertation award, three Intel patent recognition awards, seven Intel divisional recognition awards for successful technology transfers, 2015 IEEE Circuit and Systems (CAS) Society’s Transactions on VLSI systems best paper award, and 2015 SRC outstanding industrial liaison award. He has participated in technical program committees of A-SSCC, ISLPED, ISCAS, and ASQED conferences. He is serving as a technical program co-chair for 2017 ISLPED, an associate editor for IEEE Transactions on VLSI Systems, an industrial distinguished lecturer for IEEE CAS society, and as an industrial liaison for SRC, NSF, Stanford System-X alliance, Stanford-NMTRI and STARnet research programs. He is a senior member of IEEE.