The adaptive decision feedback equalizer (ADFE) constitutes an important class of equalizers, specially for multipath channels which often exhibit spectral nulls. An ADFE employs a feedforward filter (FFF) to cancel the postcursor inter symbol interference (ISI) from the received data. The residual precursor ISI is then eliminated by passing the past decisions through a feedback filter (FBF) and subtracting the FBF output from the FFF output. Since the channel is often unknown and is also time varying, adaptive techniques are used to train the FFF and the FBF coefficients. A common problem often faced by the ADFE is the floating point (FP) nature of its input, caused by the need to preamplify the weak received signal for maximum utilization of the ADC dynamic range. This is usually done by a programmable gain amplifier (PGA) which continuously adjusts its gain by power of 2 to adapt to the fluctuating signal level. A FP based processing, however, results in high processing complexity and cost. In this seminar, we propose an alternative scheme of realization using the block floating point (BFP) format. In BFP, a common exponent is assigned to a group of variables. As a result, computations involving them require simple fixed point operations, while presence of the exponent provides a FP like high dynamic range. This seminar will develop a BFP-based ADFE, by first proposing an appropriate BFP format for the input and algorithm to realize that. Separate BFP formats will be adopted for the FFF and the FBF coefficients, and update relations will be developed for their respective mantissas as well as exponents. Care will be taken to prevent overflow in all computations, by using a dynamic scaling of the data and a carefully chosen upper bound on the step size. Since no block processing is possible for the FBF input, an efficient scheme will be presented for block formatting the data stored in the FBF barrel at each time index. Computational savings vis-à-vis the FP based processing will be highlighted.

Host: Joseph Cavallaro (cavallar@rice.edu)

Biography of Mrityunjoy Chakraborty:
Mrityunjoy Chakraborty obtained Bachelor of Engg. from Jadavpur university, Calcutta in Electronics and Telecommunication Engg. (1983), followed by Master of Technology and Ph.D., both in Electrical Engg. from IIT, Kanpur (1985) and IIT, Delhi (1994) respectively. He joined IIT, Kharagpur as a faculty member in 1994, where he currently holds the position of a professor in Electronics and Electrical Communication Engg. The teaching and research interests of Prof. Chakraborty are in Digital and Adaptive Signal Processing, including algorithm, architecture and implementation, VLSI signal processing, and DSP applications in wireless communications. In these areas, Prof. Chakraborty has supervised several graduate theses, carried out independent research and has several well cited publications.

Prof. Chakraborty has been an Associate Editor of the IEEE Transactions on Circuits and Systems I during 2004-2005 and also during 2006-2007, is a guest editor for an upcoming special issue of the EURASIP JASP on distributed space time systems and has been in the technical committee of many top ranking international conferences. He has visited many well known universities overseas on invitation, including Kyoto University, Japan on a JSPS fellowship. He is a fellow of the IETE and a senior member, IEEE.